跳转至

QubitAligner

QuICT.algorithm.tools.QubitAligner 

QubitAligner(work_bits: List[int], ancilla_bits: List[int])

Align CompositeGate's working qubits and ancilla qubits with some given quantum registers given as two lists representing the work_bits register and the ancilla register.

Source code in QuICT/algorithm/tools/qubit_aligner.py 
 9
10
11
12
def __init__(self, work_bits: List[int], ancilla_bits: List[int]) -> None:
    self._check_valid_reg(work_bits, ancilla_bits)
    self._work_bits = work_bits
    self._ancilla_bits = ancilla_bits

getMap 

getMap(cg: CompositeGate, fix_top: int = 0, leave_fix_empty: bool = True) -> List[int]

Given a composite, calculate the desired application indices that will align the composite's ancilla qubits with given ancilla_bits list.

Parameters:

  • cg (CompositeGate) –

    the composite waiting to be aligned. Make sure its ancilla qubits is set as desired by using .set_ancilla() method.

  • fix_top (int, default: 0 ) –

    the number of qubits from the top that wanted to be fixed and not remapped to neither work_bits nor ancilla_bits list.

  • leave_fix_empty (bool, default: True ) –

    If True, the indices of the fix top qubits will not be in the result. If False, the indices of the fix top qubits will be set to -1.

Returns:

  • List[int] –

    List[int]: the remapped indices. In the [work_bits_indices, ancilla_indices] order.

Source code in QuICT/algorithm/tools/qubit_aligner.py 
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
def getMap(self, cg: CompositeGate, fix_top: int = 0, leave_fix_empty: bool = True) -> List[int]:
    """ Given a composite, calculate the desired application indices that will align
    the composite's ancilla qubits with given ancilla_bits list.

    Args:
        cg (CompositeGate): the composite waiting to be aligned. Make sure its ancilla qubits
            is set as desired by using `.set_ancilla()` method.
        fix_top (int): the number of qubits from the top that wanted to be fixed and not remapped to
            neither work_bits nor ancilla_bits list.
        leave_fix_empty (bool): If `True`, the indices of the fix top qubits will not be in the result.
            If `False`, the indices of the fix top qubits will be set to `-1`.

    Returns:
        List[int]: the remapped indices. In the [work_bits_indices, ancilla_indices] order.
    """
    required_width = max(cg.qubits) + 1
    work_bits_req = required_width - len(cg.ancilla_qubits) - fix_top
    if len(cg.ancilla_qubits) > len(self._ancilla_bits):
        raise ValueError("Not enough ancilla bits for the input composite gate. "
                         f"Given {len(self._ancilla_bits)} but the gate requires {len(cg.ancilla_qubits)}.")
    if work_bits_req > len(self._work_bits):
        raise ValueError("Not enough work qubits for the input composite gate. "
                         f"Given {len(self._work_bits)} but the gate requires {work_bits_req}.")
    for i in list(range(fix_top)):
        if i in cg.ancilla_qubits:
            raise ValueError(f"Cannot set {i}th qubits to be fixed for it appears in composite gate's "
                             f"ancilla_qubits list: {cg.ancilla_qubits}.")

    # iterate both register from top to bottom
    it_ancilla = 0
    it_work = len(self._work_bits) - work_bits_req
    final_map = []
    for i in range(fix_top, required_width):
        if i in cg.ancilla_qubits:
            idx = self._ancilla_bits[it_ancilla]
            it_ancilla += 1
        else:
            idx = self._work_bits[it_work]
            it_work += 1
        final_map.append(idx)

    if leave_fix_empty:
        return final_map

    return [-1] * fix_top + final_map